Direct Bonding

The Direct Metallic Bonding method is used to assemble two components.

Despite its main difficulty -components must have a very high level of cleanliness, there are several reasons to use Direct Metallic Bonding. The three main reasons are: low bonding force, bonding process at room temperature and short process cycle.

Thus, it ensures high precision, in particular by avoiding differences in thermal expansion coefficients between different materials.
This all makes Direct Metallic Bonding an excellent candidate for advanced chip-to-wafer technologies applicable to 3D integration.

PROCEED PROJECT

2009: started by Minalogic with the support of the French government (FUI – Fond Unique Interministériel)

Objective: prove that high precision chip-to-wafer positioning (< 1μm) is possible when using Direct Metallic Bonding.

In partnership with CEA-Leti, ST-Microelectronics, ALES and CEMES-CNR, SET successfully demonstrated the feasibility of Direct Metallic Bonding, thanks to a specially designed FC300. This success was the subject of numerous articles

IRT Nanoelec

End of 2015: SET worked with IRT Nanoelec to design a rapid high precision machine that uses the Direct Metallic Bonding method.

Capitalizing on the experience of the PROCEED project, SET designed and developed the NEO HB, specially dedicated to direct bonding production.

September 2019: SET launched the NEO HB at SEMICON Taiwan, thus meeting the high throughput needs necessary for widespread adoption of 3D integration.

PROCEED Project

The PROCEED Minalogic project is a 4.2 Million Euros, 24 months project supported by French FIU (Fond Interministeriel Unique). Started in 2009, the goal of the PROCEED project is to demonstrate high alignment accuracy (< 1 µm) of chip-to-wafer structures made by direct metallic bonding. Such structures are required for high performance 3D interconnexion circuits and enable a wide range of applications in microelectronics as well as in optoelectronics or MEMS.

Direct copper-to-copper bonding requires good planarity and excellent surface quality especially in terms of both particulate and metallic contamination. The low roughness of the copper pillars and pads as well as the topography between the copper and oxide areas are critical to obtain good bond strength at low force and room temperature.

The process, based on chip-to-wafer direct metallic bonding, is developed at CEA-Leti to overcome certain limitations in 3D integration. This technology consists of attaching chips on a substrate at low temperature and force, creating a bond of high mechanical and electrical integrity due to local metallic bonding.

ALES supplys technology to support the surface preparation while CEMES-CNRS characterizes the bond quality and analyzes changes to the copper metallurgy during the annealing step. STMicroelectronics is driving the application of this technology for the high density 3D integration.

Technology Benefits

This direct metal-to-metal bonding technology offers many advantages compare to conventional thermo-compression bonding.

The bonding process takes place at low force and room temperature, enabling higher accuracy bonding for high density interconnections by circumventing thermal expansion of differing materials. To ensure void-free bonding, the alignment and bonding steps must take place in a particle-free environment. It is accomplished by the use of special materials and careful management of the bonding environment to protect the wafer surface while it is fully populated with dice.

A low-force bonding process is key to the high throughput required for widespread adoption of 3D IC Integration.

Technical Papers

TITLE

DATE

FROM

Chip-to-Wafer Technologies for High Density 3D Integration

May 2011

CEA Leti Minatec, ALES, STMicroelectronics, CNRS-CEMES, SET

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