Shorten connections lengths to reduce electrical resistance, improve response time as well as reduce power consumption and overall dimensions are the main goals of 3D-IC integration.
It enables the high yielding assembly of heterogeneous devices. There are numerous 3D packaging solutions such as:
The post-bonding accuracy requirement varies with the application.
Through-Silicon-Via (TSV) is one of the most promising interconnection between chip layers. The reduction of the TSV diameter and the increase of the pitch imply higher accuracy, not only along X and Y axes, but also in the parallelism between chips.