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The main goals of 3D-IC Integration are to shorten connections lengths, reduce electrical resistance, improve response time and reduce power consumption and overall dimensions. This enables the high-yield assembly of devices and facilitates effective 3D packaging solutions, such as:

• Interposer
• Chip-to-Chip
• Chip-to-Wafer

The post-bonding accuracy requirement varies by application.

Through-Silicon-Via (TSV) is one of the most promising interconnection methods between chip layers. The reduction of TSV diameter and increase of pitch imply higher accuracy, not just along X and Y axes but also in the parallelism between chips.